1. Field of the Invention
The invention relates to a method of manufacturing a semiconductor device having damascene structures with air gaps as well as to a semiconductor device thus manufactured.
2. Description of the Related Technology
The trend towards integrated circuits with deep submicron technology (i.e., involving feature sizes of less than 0.35 microns) has increased the need for multi-layer interconnects. The performance of integrated circuits in the deep submicron regime is increasingly dependent on the communication delay, i.e., the delay time of electronic signals traveling between the millions of gates and transistors present on the typical integrated circuits. As a result, capacitance and resistance effects resulting from the passive interconnect structures are increasingly becoming important and do have to be well-controlled.
One way to solve the above problems is to use low resistance metals (e.g., copper) in conjunction with insulating materials with low dielectric constants (“low-k dielectrics”) between metal lines. A low-k dielectric is a dielectric material which exhibits a substantially lower dielectric constant than conventional dielectric materials such as silicon dioxide.
Based on considerable efforts optical lithography techniques have been able to keep up with deep submicron requirements using techniques such as off-axis illumination, phase shifting masks, and other methods known in the art. However, the achieved increase in resolution comes at the expense of a decrease in the depth of focus. Therefore, highly planar surfaces are required during intermediary process steps. To achieve highly planar surfaces, traditional metal deposition and photolithographic techniques become progressively more ineffective as line widths are scaled down and multiple layers of metal are used.
Chemical-Mechanical Polishing (CMP) is increasingly being used in the fabrication of interconnect layers for modern integrated circuits especially with more than three layers. The metal lines thereof usually comprise a high aspect ratio (e.g., lines in the order of 0.25 μm in width and in the order of 1.0 μm in height). For more details on CMP please refer to the introductory part of U.S. Pat. No. 6,071,809.
A typical semiconductor manufacturing technique based on CMP techniques is the so-called damascene process. A damascene process comprises the steps of forming patterns in a dielectric layer, filling these patterns with an interconnect metal, removing the excess metal on the wafer surface by polishing and leaving inlaid interconnect metal features.
Basically two damascene processes exist, namely the single-damascene and the dual-damascene process. In a single damascene process, a lower conductor is formed on a substrate and is coated with a first dielectric layer. The lower conductor is contacted by patterning the first dielectric layer and forming a conductive plug in the first dielectric layer. Thereafter, a second dielectric layer deposited on the first dielectric layer is patterned and an interconnect wiring metallization is formed in the patterned second dielectric layer. In addition a dielectric is deposited, the structures are etched and the metal is filled and planarized resulting in inlaid metal structures. During the fabrication and the interconnecting using single damascene processing, every layer is formed separately, i.e., a single damascene trench level followed by single damascene via level. However, in a dual-damascene process, the interconnect metal wiring and the conductive plug are formed by patterning both the via and the trench patterns into the first dielectric layer. Thereafter, the via and the trench are filled simultaneously with metal. The dual damascene process provides a simple and low-cost manufacturing technique.
Copper is preferred over aluminum for interconnect metallization as its conductivity is relatively high, i.e., low resistance, and it is less susceptible to electro-migration failure than many other metals. On the other hand, the use of Cu as interconnect metal introduces new problems, since bringing copper into contact with silicon or silicon dioxide may lead to devastating results. This is because copper migrates or diffuses into the silicon dioxide, thereby increasing leakage currents or actually shorting-out adjacent conductors. Accordingly, some kind of Cu diffusion barriers around copper conductors must be introduced. In the above damascene structures, the inner surfaces (i.e., the bottom and sides of the via and trench) are typically coated with a thin layer of Ti, TiN, Ta, TaN, WN or another adequate barrier metal. The top surface of a Cu conductor is then typically capped with a layer of silicon nitride or another barrier material after the inlaid Cu conductors are formed by CMP. Silicon nitride, silicon carbide or silicon carbonitride is typically used as it is an effective diffusion barrier for copper.
In U.S. Pat. No. 6,071,809 a typical prior art low-k dual-damascene structure is shown, which includes copper conductors formed on a substrate with a dielectric (e.g., silicon dioxide or a low-k dielectric). A nitride cap layer is formed on copper conductors, which is followed by a low-k dielectric layer, an etch stop silicon dioxide layer, a second low-k dielectric layer, and a hard mask silicon dioxide layer. Using standard etching techniques, vias and trenches are patterned in the low-k dielectrics, and the copper interconnect metal and any seed and barrier layers are deposited to form the connection to conductors. The cap layer typically consists of silicon nitride and the hard mask layer typically consists of silicon dioxide.
Usually, advanced low-k materials have a bulk k-value of approximately 2, while air has a k-value of 1. Therefore, the use of air gaps instead of low-k materials would lead to a significant reduction of parasitic capacitance. One example of a damascene structure with air gaps is shown in WO 02/19416. A standard dual damascene structure is manufactured as described in U.S. Pat. No. 6,071,809. The dual damascene structure comprises a metal layer, a first dielectric layer as via dielectric (low-k dielectrics such as siloxane or a polyarylene ether), a second dielectric layer (such as SOG, Nanoglass™ or a polymer like SiLK) disposed on the first dielectric layer as trench level dielectric with an interconnect groove. In addition, an etch stop layer (such as SiN) is present between the first dielectric layer and the second dielectric layer. Metal, preferably copper (Cu), fills the via and the interconnect groove, forming a metal line having an upper side. A barrier and the Cu seed layer is provided on the walls of the via and the interconnect groove before depositing the Cu. The second dielectric layer is removed so that the metal which has filled the interconnect grove at trench level is laid open, i.e., the second dielectric layer is used as a sacrificial layer for defining the metal lines. A non-conductive barrier layer (such as silicon nitride or silicon carbide) is provided over the laid open metal line and the laid open etch stop layer. A disposable layer is deposited on the etch stop layer and the metal line. Thereafter, the disposable layer is planarized down to the upper side of the metal line. A porous dielectric layer is spun on the disposable layer, and the disposable layer is removed or decomposed through the porous dielectric layer in order to form air gaps. The air gaps are obtained through a curing and baking step possibly assisted with UV treatment.
The spin-on material of the porous dielectric layer comprises a polymer which can be volatilized or degraded to smaller molecules, like PMMA (polymethyl methacrylate), polystyrene, and polyvinyl alcohol. Alternatively, a UV photoresist may also be used as the basic material for the manufacture of air gaps, and a plasma CVD layer or a spin-on dielectric layer is used for the porous dielectric layer. The porous dielectric layer preferably comprises a low-k dielectric such as SiLK, provided in a spin coating process. A plasma CVD layer may also be used as the porous dielectric layer.